The present invention relates to a memory circuit, and more particularly is related to a non-volatile memory circuit.
BACKGROUND OF THE INVENTION
Integrated circuit memories have come into extensive use in many applications, particularly for computer systems. It has been a pronounced technological trend to increase the capacity and density of such memories. As manufacturing and design techniques have improved, the cost of memory circuits has decreased dramatically, and this has greatly expanded the number of applications and the size of the market. There are essentially two types of data memory devices used in computers today, xe2x80x9cNonvolatilexe2x80x9d and xe2x80x9cVolatilexe2x80x9d. Common nonvolatile memory devices include well known Read Only Memory (ROM) devices that include EPROM (erasable programmable ROM) devices, EEPROM (electrically erasable programmable ROM) devices, and Flash EEPROM devices. These nonvolatile memory devices maintain the data stored therein, even when power to the device is removed, and thus they are nonvolatile. Volatile memory devices include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) devices. This distinction generally follows from the type of memory cell incorporated in the RAM. In the case of a dynamic RAM memory cell, data is stored in a capacitor. Because the charge is stored in a capacitor in the substrate, the charge dissipates and needs to be refreshed periodically in order to preserve the content of the memory. Static RAMS differ from dynamic RAMS by having memory cells which do not need to be refreshed. A static RAM cell usually includes several MOS transistors configured as a flip-flop which has two stable states. These two states are used for storing the two different levels of binary data. Static RAM cells, because they include several transistors, are larger than DRAM cells and therefore cannot be packed as densely on semiconductor chips. On the other hand, static RAMS operate quickly and do not require the logic circuitry needed for refresh operations.
FIG. 1 illustrates a circuit diagram of a conventional static RAM 100. The static AM 100 includes two n-channel MOS transistors 104, 105 and two p-channel MOS transistors 106, 107. A pair of nodes A and B is cross coupled to the gate electrodes of MOS transistors 104 to 107 (flip-flop structure). This cross-coupled arrangement produces a regenerative effect which drive the nodes A and B to opposite voltage states. When one node is high the other is low. The circuit 100 therefore has two data states. A node C is set at the Vss level of zero volts. A further node D couples to a full Vdd source. The source-drain paths of access MOS transistors 108 and 109 couple internal nodes A and B, respectively, to bit lines 102 and 103. The gate electrodes of access MOS transistors 108 and 109 are coupled to word line 101.
FIG. 2 illustrates a reading and writing waveform diagram of a static RAM 100. When writing logic xe2x80x9c1xe2x80x9d into the static RAM 100, the voltage state of word line 101 and bit line 102 are maintained at a high level. The high state at node B causes MOS transistor 107 to be turned off and MOS transistor 105 to be turned on. This pulls node A to a low voltage state; bit line 103 is also in a low voltage state. The low state at node A permits MOS transistor 106 to be on while holding MOS transistor 104 turned off. This further causes node B to be pulled to a high voltage state through MOS transistor 106. A logic xe2x80x9c1xe2x80x9d state for the static RAM 100 is arbitrarily defined to be node B high and node A low. When reading logic xe2x80x9c1xe2x80x9d from the static RAM 100, bit lines 103 and 102 are first set in predetermine voltage state. Then, a high voltage is applied to the word line 101. At this time, the predetermined voltage state of bit line 103 is pulled down from MOS transistors 105 and 109. A data reading circuit (not shown in FIG. 2) detects a voltage difference between the bit line 102 and 103 and enlarges the difference to read out the stored data, logic xe2x80x9c1xe2x80x9d.
When writing logic xe2x80x9c0xe2x80x9d into the static RAM 100, the voltage state of word line 101 and bit line 103 are maintained at a high level. The high state at node A causes MOS transistor 106 to be turned off and MOS transistor 104 to be turned on. This pulls node B to a low voltage state and bit line 102 is also in low voltage state. The low state at node B permits MOS transistor 107 to be on while holding MOS transistor 105 is turned off. This further causes node A to be pulled to a high voltage state through MOS transistor 107. A logic xe2x80x9c0xe2x80x9d state for the static RAM 100 is arbitrarily defined to be node A high and node B low. When reading logic xe2x80x9c0xe2x80x9d from the static RAM 100, bit lines 103 and 102 are first set to a predetermined voltage state. Then, a high voltage is applied to the word line 101. At this time, the predetermined voltage state of bit line 102 is pulled down from MOS transistors 104 and 108. A data reading circuit (not shown in FIG. 2) detects a voltage difference between bit lines 102 and 103 and enlarges the difference to read out the stored data, logic xe2x80x9c0xe2x80x9d.
However, the low cost, large capacity static RAM circuits now in use have volatile memory storage, that is, the data stored in these memories is lost when the power is removed. There are many applications that could be enhanced if low cost, non-volatile memories could be made. In certain applications, it is essential that the data be retained in the memory when power is removed. To fill this market, several types of non-volatile memories have been developed. Among the most common of these now in use is the electronically programmable read only memory (EPROM). However, the non-volatile memories now available typically have a rather low density of memory storage, are generally complex to manufacture, often have a limited lifetime and are much more expensive than volatile memories. Therefore, from the foregoing, it can be seen that a need exists for non-volatile memory storage having low cost and high density of memory storage.
The conventional static RAMS, while having the advantage of being randomly accessible, have the disadvantage of being volatile. That is, when power is removed from the memories, the data dissipates. The voltage used to preserve the flip-flop states in the static RAM memory cells drops to zero so that the flip-flop loses its data. Therefore, the static RAMS according to the present invention uses ferroelectric capacitors for memory cells that have a significant advantage of being non-volatile. Briefly, a ferroelectric capacitor includes a pair of capacitor plates with a ferroelectric material between them. A ferroelectric material has two different stable polarization states and can store the polarization state even though the applied voltage is removed. By assigning a binary zero to one polarization state and a binary one to the other polarization state, ferroelectric capacitors can be used to store binary information. Therefore, according to the present invention, the data of the static RAMS is restored into the ferroelectric capacitors. The advantage of this arrangement is that even though power may be interrupted or removed from the memory, data continues to be stored.
According to the present invention providing a new memory circuit design, a conventional static RAMS is combined with a ferroelectric capacitors circuit, which takes these advantages of non-volatile characteristics and providing fast, random writing and reading of data for such circuits. The memory circuit according to the present invention comprises two MOS transistor circuits to form a CMOS flip-flop circuit and two ferroelectric capacitors According to the preferred embodiment, the MOS transistor circuit is composed of both a P type MOS transistor and an N type transistor. The two circuits have respectively a common node, and the two common nodes are cross-coupled for producing differential voltage states at the two nodes, respectively. Each MOS transistor circuit couples with a ferroelectric capacitor. The two ferroelectric capacitors are connected together by a MOS transistor and connected to a plate line through another transistor. The two ferroelectric capacitors are used to store data when power may be removed from the memory circuit.
During a writing operation, a voltage is applied to the plate line to result in the voltage difference between the plate line and the two common nodes. Thus, the two ferroelectric capacitors are set to have differential polarization states to store data. During a reading operation, approximately one half of Vcc is applied to the two common nodes. Then, a Vcc voltage is applied to the plate line that causes a charge transfer across the two ferroelectric capacitors into the nodes respectively. At the time of the voltage Vcc at plate line, a transition in the polarization state of one of the two ferroelectric capacitors is caused because the voltage at the plate line is opposite to the polarization state of the capacitor, therefore, there is a net charge shift in current. This situation causes the unbalanced condition of the two common nodes, thereby reestablishing the previous data state in the memory circuit.